Static Timing Analysis

Project : 8000_Series_Swiss_Army_Knife
Build Time : 08/11/17 19:22:41
Device : CY8C5888LTI-LP097
Temperature : 0C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_1_theACLK(routed) ADC_SAR_1_theACLK(routed) 9.600 MHz 9.600 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz 93.809 MHz
emFile_1_Clock_1 CyMASTER_CLK 48.000 MHz 48.000 MHz 65.325 MHz
ADC_SAR_1_theACLK CyMASTER_CLK 9.600 MHz 9.600 MHz N/A
SPIM_1_Clock CyMASTER_CLK 1.000 MHz 1.000 MHz 53.576 MHz
UART_1_Clock CyMASTER_CLK 76.800 kHz 76.800 kHz 65.415 MHz
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)_SYNC/out \UART_1:BUART:sRX:RxShifter:u0\/route_si 93.809 MHz 10.660 10.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_postpoll\/main_2 3.073
macrocell25 U(1,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 2.345
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.102
datapathcell3 U(1,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 2.430
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 159.898 MHz 6.254 14.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.087
macrocell43 U(1,1) 1 \UART_1:BUART:rx_state_0\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 159.898 MHz 6.254 14.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 3.087
macrocell52 U(1,1) 1 \UART_1:BUART:rx_status_3\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 160.256 MHz 6.240 14.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.073
macrocell46 U(0,1) 1 \UART_1:BUART:rx_state_2\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 160.256 MHz 6.240 14.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 3.073
macrocell49 U(1,1) 1 \UART_1:BUART:pollcount_1\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 160.256 MHz 6.240 14.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 3.073
macrocell50 U(1,1) 1 \UART_1:BUART:pollcount_0\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 160.256 MHz 6.240 14.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 3.073
macrocell53 U(0,1) 1 \UART_1:BUART:rx_last\ SETUP 2.457
Clock Skew 0.000
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:TxStsReg\/status_0 53.576 MHz 18.665 981.335
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell56 U(2,1) 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/clock_0 \SPIM_1:BSPIM:state_2\/q 0.875
Route 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:tx_status_0\/main_0 9.067
macrocell29 U(1,3) 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/main_0 \SPIM_1:BSPIM:tx_status_0\/q 2.345
Route 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 6.028
statusicell3 U(2,4) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.350
Clock Skew 0.000
\SPIM_1:BSPIM:state_1\/q \SPIM_1:BSPIM:TxStsReg\/status_0 53.616 MHz 18.651 981.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell57 U(2,1) 1 \SPIM_1:BSPIM:state_1\ \SPIM_1:BSPIM:state_1\/clock_0 \SPIM_1:BSPIM:state_1\/q 0.875
Route 1 \SPIM_1:BSPIM:state_1\ \SPIM_1:BSPIM:state_1\/q \SPIM_1:BSPIM:tx_status_0\/main_1 9.053
macrocell29 U(1,3) 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/main_1 \SPIM_1:BSPIM:tx_status_0\/q 2.345
Route 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 6.028
statusicell3 U(2,4) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.350
Clock Skew 0.000
\SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 58.727 MHz 17.028 982.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(1,0) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/clock_0 \SPIM_1:BSPIM:state_0\/q 0.875
Route 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:tx_status_0\/main_2 7.430
macrocell29 U(1,3) 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/main_2 \SPIM_1:BSPIM:tx_status_0\/q 2.345
Route 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 6.028
statusicell3 U(2,4) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.350
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 65.625 MHz 15.238 984.762
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 1.360
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:load_rx_data\/main_2 3.289
macrocell28 U(2,3) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_2 \SPIM_1:BSPIM:load_rx_data\/q 2.345
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 6.244
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_2 67.322 MHz 14.854 985.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell56 U(2,1) 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/clock_0 \SPIM_1:BSPIM:state_2\/q 0.875
Route 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_2 9.769
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 4.210
Clock Skew 0.000
\SPIM_1:BSPIM:state_1\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_1 67.372 MHz 14.843 985.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell57 U(2,1) 1 \SPIM_1:BSPIM:state_1\ \SPIM_1:BSPIM:state_1\/clock_0 \SPIM_1:BSPIM:state_1\/q 0.875
Route 1 \SPIM_1:BSPIM:state_1\ \SPIM_1:BSPIM:state_1\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_1 9.758
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 4.210
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 68.129 MHz 14.678 985.322
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 1.360
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:load_rx_data\/main_1 2.729
macrocell28 U(2,3) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_1 \SPIM_1:BSPIM:load_rx_data\/q 2.345
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 6.244
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 68.828 MHz 14.529 985.471
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 1.360
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 2.580
macrocell28 U(2,3) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 2.345
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 6.244
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 69.672 MHz 14.353 985.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 1.360
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_rx_data\/main_3 2.404
macrocell28 U(2,3) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_3 \SPIM_1:BSPIM:load_rx_data\/q 2.345
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 6.244
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 69.740 MHz 14.339 985.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 1.360
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:load_rx_data\/main_4 2.390
macrocell28 U(2,3) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_4 \SPIM_1:BSPIM:load_rx_data\/q 2.345
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 6.244
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
Path Delay Requirement : 13020.8ns(76.8 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 65.415 MHz 15.287 13005.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(1,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 0.875
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 6.265
macrocell24 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.042
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 68.535 MHz 14.591 13006.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(3,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 0.875
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 4.958
macrocell21 U(3,2) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 2.345
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.083
datapathcell2 U(3,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 4.330
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 72.239 MHz 13.843 13006.990
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(3,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 0.875
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 4.210
macrocell21 U(3,2) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 2.345
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.083
datapathcell2 U(3,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 4.330
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 74.800 MHz 13.369 13007.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell46 U(0,1) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 0.875
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 4.347
macrocell24 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.042
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 76.173 MHz 13.128 13007.705
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(3,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 0.875
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 3.495
macrocell21 U(3,2) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 2.345
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.083
datapathcell2 U(3,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 4.330
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 77.024 MHz 12.983 13007.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(1,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 0.875
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 7.898
datapathcell3 U(1,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 4.210
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 79.586 MHz 12.565 13008.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell45 U(0,0) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 0.875
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 3.543
macrocell24 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.042
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 81.719 MHz 12.237 13008.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell42 U(0,0) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 0.875
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 3.215
macrocell24 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.042
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 84.724 MHz 11.803 13009.030
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(3,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 0.875
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 6.718
datapathcell1 U(3,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 4.210
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_state_0\/main_1 84.832 MHz 11.788 13009.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(1,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 0.875
macrocell43 U(1,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_state_0\/main_1 8.456
macrocell43 U(1,1) 1 \UART_1:BUART:rx_state_0\ SETUP 2.457
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\emFile_1:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_0 65.325 MHz 15.308 5.525
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/clock \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/so_comb 3.750
Route 1 \emFile_1:SPI0:BSPIM:mosi_from_dp\ \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/main_3 4.054
macrocell1 U(3,4) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/main_3 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_0 2.702
macrocell68 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg\ SETUP 2.457
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:state_1\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_1 69.828 MHz 14.321 6.512
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell64 U(2,5) 1 \emFile_1:SPI0:BSPIM:state_1\ \emFile_1:SPI0:BSPIM:state_1\/clock_0 \emFile_1:SPI0:BSPIM:state_1\/q 0.875
Route 1 \emFile_1:SPI0:BSPIM:state_1\ \emFile_1:SPI0:BSPIM:state_1\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/main_1 6.570
macrocell51 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/main_1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_1 2.074
macrocell68 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg\ SETUP 2.457
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:state_1\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_0 70.121 MHz 14.261 6.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell64 U(2,5) 1 \emFile_1:SPI0:BSPIM:state_1\ \emFile_1:SPI0:BSPIM:state_1\/clock_0 \emFile_1:SPI0:BSPIM:state_1\/q 0.875
Route 1 \emFile_1:SPI0:BSPIM:state_1\ \emFile_1:SPI0:BSPIM:state_1\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/main_1 5.882
macrocell1 U(3,4) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/main_1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_0 2.702
macrocell68 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg\ SETUP 2.457
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_1 72.606 MHz 13.773 7.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/clock \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/so_comb 3.750
Route 1 \emFile_1:SPI0:BSPIM:mosi_from_dp\ \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/main_3 3.147
macrocell51 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/main_3 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_1 2.074
macrocell68 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg\ SETUP 2.457
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_2 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 77.664 MHz 12.876 7.957
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_2 1.360
Route 1 \emFile_1:SPI0:BSPIM:count_2\ \emFile_1:SPI0:BSPIM:BitCounter\/count_2 \emFile_1:SPI0:BSPIM:load_rx_data\/main_2 4.610
macrocell32 U(2,2) 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/main_2 \emFile_1:SPI0:BSPIM:load_rx_data\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/q \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 2.561
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \emFile_1:SPI0:BSPIM:RxStsReg\/status_6 78.364 MHz 12.761 8.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/clock \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 2.510
Route 1 \emFile_1:SPI0:BSPIM:rx_status_4\ \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \emFile_1:SPI0:BSPIM:rx_status_6\/main_5 5.458
macrocell36 U(2,5) 1 \emFile_1:SPI0:BSPIM:rx_status_6\ \emFile_1:SPI0:BSPIM:rx_status_6\/main_5 \emFile_1:SPI0:BSPIM:rx_status_6\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:rx_status_6\ \emFile_1:SPI0:BSPIM:rx_status_6\/q \emFile_1:SPI0:BSPIM:RxStsReg\/status_6 2.098
statusicell6 U(2,5) 1 \emFile_1:SPI0:BSPIM:RxStsReg\ SETUP 0.350
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_4 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 78.616 MHz 12.720 8.113
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_4 1.360
Route 1 \emFile_1:SPI0:BSPIM:count_4\ \emFile_1:SPI0:BSPIM:BitCounter\/count_4 \emFile_1:SPI0:BSPIM:load_rx_data\/main_0 4.454
macrocell32 U(2,2) 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/main_0 \emFile_1:SPI0:BSPIM:load_rx_data\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/q \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 2.561
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_0 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 78.753 MHz 12.698 8.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_0 1.360
Route 1 \emFile_1:SPI0:BSPIM:count_0\ \emFile_1:SPI0:BSPIM:BitCounter\/count_0 \emFile_1:SPI0:BSPIM:load_rx_data\/main_4 4.432
macrocell32 U(2,2) 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/main_4 \emFile_1:SPI0:BSPIM:load_rx_data\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/q \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 2.561
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:ld_ident\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_1 79.133 MHz 12.637 8.196
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell71 U(3,5) 1 \emFile_1:SPI0:BSPIM:ld_ident\ \emFile_1:SPI0:BSPIM:ld_ident\/clock_0 \emFile_1:SPI0:BSPIM:ld_ident\/q 0.875
Route 1 \emFile_1:SPI0:BSPIM:ld_ident\ \emFile_1:SPI0:BSPIM:ld_ident\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/main_9 4.886
macrocell51 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/main_9 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile_1:SPI0:BSPIM:mosi_pre_reg\/main_1 2.074
macrocell68 U(3,3) 1 \emFile_1:SPI0:BSPIM:mosi_pre_reg\ SETUP 2.457
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_3 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 79.904 MHz 12.515 8.318
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_3 1.360
Route 1 \emFile_1:SPI0:BSPIM:count_3\ \emFile_1:SPI0:BSPIM:BitCounter\/count_3 \emFile_1:SPI0:BSPIM:load_rx_data\/main_1 4.249
macrocell32 U(2,2) 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/main_1 \emFile_1:SPI0:BSPIM:load_rx_data\/q 2.345
Route 1 \emFile_1:SPI0:BSPIM:load_rx_data\ \emFile_1:SPI0:BSPIM:load_rx_data\/q \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/f1_load 2.561
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.000
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.073
macrocell46 U(0,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 3.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 3.073
macrocell49 U(1,1) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 3.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 3.073
macrocell50 U(1,1) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 3.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 3.073
macrocell53 U(0,1) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.087
macrocell43 U(1,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 3.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 3.087
macrocell52 U(1,1) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:sRX:RxShifter:u0\/route_si 7.770
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,1) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_postpoll\/main_2 3.073
macrocell25 U(1,1) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 2.345
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.102
datapathcell3 U(1,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM_1:BSPIM:BitCounter\/count_0 Net_23/main_9 2.829
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 0.430
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 Net_23/main_9 2.399
macrocell55 U(2,3) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 Net_23/main_8 2.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 0.430
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 Net_23/main_8 2.415
macrocell55 U(2,3) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 2.953
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell60 U(2,4) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/clock_0 \SPIM_1:BSPIM:load_cond\/q 0.875
macrocell60 U(2,4) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 2.078
macrocell60 U(2,4) 1 \SPIM_1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
Net_638/q Net_638/main_3 2.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell59 U(0,3) 1 Net_638 Net_638/clock_0 Net_638/q 0.875
macrocell59 U(0,3) 1 Net_638 Net_638/q Net_638/main_3 2.094
macrocell59 U(0,3) 1 Net_638 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_2\/main_9 2.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell61 U(2,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 0.875
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_2\/main_9 2.094
macrocell56 U(2,1) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_1\/main_9 2.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell61 U(2,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 0.875
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_1\/main_9 2.094
macrocell57 U(2,1) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:ld_ident\/main_8 2.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell61 U(2,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 0.875
macrocell61 U(2,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:ld_ident\/main_8 2.094
macrocell61 U(2,1) 1 \SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 Net_23/main_5 3.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 0.430
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 Net_23/main_5 2.602
macrocell55 U(2,3) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 Net_23/main_6 3.167
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 0.430
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 Net_23/main_6 2.737
macrocell55 U(2,3) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:state_0\/main_2 3.188
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(1,0) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/clock_0 \SPIM_1:BSPIM:state_0\/q 0.875
macrocell58 U(1,0) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:state_0\/main_2 2.313
macrocell58 U(1,0) 1 \SPIM_1:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.195
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(1,1) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 0.875
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.720
statusicell2 U(1,2) 1 \UART_1:BUART:sRX:RxSts\ HOLD -1.400
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.454
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_0 0.430
Route 1 \UART_1:BUART:rx_count_0\ \UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.024
macrocell47 U(0,0) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_3\/main_7 2.473
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.430
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_3\/main_7 2.043
macrocell45 U(0,0) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.753
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.430
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.323
macrocell47 U(0,0) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.756
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.430
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.326
macrocell47 U(0,0) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 2.760
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.430
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 2.330
macrocell45 U(0,0) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.130
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.714
macrocell40 U(3,1) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_8 2.976
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell53 U(0,1) 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/clock_0 \UART_1:BUART:rx_last\/q 0.875
Route 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_8 2.101
macrocell46 U(0,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 3.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 1.060
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.033
macrocell37 U(3,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 3.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell47 U(0,0) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 0.875
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 2.299
macrocell45 U(0,0) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\emFile_1:SPI0:BSPIM:BitCounter\/count_3 \emFile_1:SPI0:BSPIM:state_2\/main_4 2.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_3 0.430
Route 1 \emFile_1:SPI0:BSPIM:count_3\ \emFile_1:SPI0:BSPIM:BitCounter\/count_3 \emFile_1:SPI0:BSPIM:state_2\/main_4 2.396
macrocell63 U(3,4) 1 \emFile_1:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:load_cond\/q \emFile_1:SPI0:BSPIM:load_cond\/main_8 2.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell69 U(2,2) 1 \emFile_1:SPI0:BSPIM:load_cond\ \emFile_1:SPI0:BSPIM:load_cond\/clock_0 \emFile_1:SPI0:BSPIM:load_cond\/q 0.875
macrocell69 U(2,2) 1 \emFile_1:SPI0:BSPIM:load_cond\ \emFile_1:SPI0:BSPIM:load_cond\/q \emFile_1:SPI0:BSPIM:load_cond\/main_8 2.090
macrocell69 U(2,2) 1 \emFile_1:SPI0:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:mosi_hs_reg\/q \emFile_1:SPI0:BSPIM:mosi_hs_reg\/main_4 2.967
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell67 U(2,2) 1 \emFile_1:SPI0:BSPIM:mosi_hs_reg\ \emFile_1:SPI0:BSPIM:mosi_hs_reg\/clock_0 \emFile_1:SPI0:BSPIM:mosi_hs_reg\/q 0.875
macrocell67 U(2,2) 1 \emFile_1:SPI0:BSPIM:mosi_hs_reg\ \emFile_1:SPI0:BSPIM:mosi_hs_reg\/q \emFile_1:SPI0:BSPIM:mosi_hs_reg\/main_4 2.092
macrocell67 U(2,2) 1 \emFile_1:SPI0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:mosi_from_dp_reg\/q \emFile_1:SPI0:BSPIM:mosi_hs_reg\/main_5 2.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell70 U(2,2) 1 \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\ \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\/clock_0 \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\/q 0.875
Route 1 \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\ \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\/q \emFile_1:SPI0:BSPIM:mosi_hs_reg\/main_5 2.097
macrocell67 U(2,2) 1 \emFile_1:SPI0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_1 \emFile_1:SPI0:BSPIM:state_2\/main_6 3.006
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_1 0.430
Route 1 \emFile_1:SPI0:BSPIM:count_1\ \emFile_1:SPI0:BSPIM:BitCounter\/count_1 \emFile_1:SPI0:BSPIM:state_2\/main_6 2.576
macrocell63 U(3,4) 1 \emFile_1:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_4 \emFile_1:SPI0:BSPIM:state_2\/main_3 3.023
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_4 0.430
Route 1 \emFile_1:SPI0:BSPIM:count_4\ \emFile_1:SPI0:BSPIM:BitCounter\/count_4 \emFile_1:SPI0:BSPIM:state_2\/main_3 2.593
macrocell63 U(3,4) 1 \emFile_1:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_0 \emFile_1:SPI0:BSPIM:state_2\/main_7 3.024
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_0 0.430
Route 1 \emFile_1:SPI0:BSPIM:count_0\ \emFile_1:SPI0:BSPIM:BitCounter\/count_0 \emFile_1:SPI0:BSPIM:state_2\/main_7 2.594
macrocell63 U(3,4) 1 \emFile_1:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile_1:Net_1\/q \emFile_1:Net_1\/main_3 3.293
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell66 U(2,5) 1 \emFile_1:Net_1\ \emFile_1:Net_1\/clock_0 \emFile_1:Net_1\/q 0.875
macrocell66 U(2,5) 1 \emFile_1:Net_1\ \emFile_1:Net_1\/q \emFile_1:Net_1\/main_3 2.418
macrocell66 U(2,5) 1 \emFile_1:Net_1\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:BitCounter\/count_2 \emFile_1:SPI0:BSPIM:state_2\/main_5 3.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile_1:SPI0:BSPIM:BitCounter\ \emFile_1:SPI0:BSPIM:BitCounter\/clock \emFile_1:SPI0:BSPIM:BitCounter\/count_2 0.430
Route 1 \emFile_1:SPI0:BSPIM:count_2\ \emFile_1:SPI0:BSPIM:BitCounter\/count_2 \emFile_1:SPI0:BSPIM:state_2\/main_5 2.893
macrocell63 U(3,4) 1 \emFile_1:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile_1:SPI0:BSPIM:state_0\/q \emFile_1:SPI0:BSPIM:ld_ident\/main_2 3.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell65 U(3,5) 1 \emFile_1:SPI0:BSPIM:state_0\ \emFile_1:SPI0:BSPIM:state_0\/clock_0 \emFile_1:SPI0:BSPIM:state_0\/q 0.875
Route 1 \emFile_1:SPI0:BSPIM:state_0\ \emFile_1:SPI0:BSPIM:state_0\/q \emFile_1:SPI0:BSPIM:ld_ident\/main_2 2.712
macrocell71 U(3,5) 1 \emFile_1:SPI0:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_1_Clock
Source Destination Delay (ns)
MISO_1(0)_PAD \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 15.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO_1(0)_PAD MISO_1(0)_PAD MISO_1(0)/pad_in 0.000
iocell22 P2[4] 1 MISO_1(0) MISO_1(0)/pad_in MISO_1(0)/fb 7.454
Route 1 Net_19 MISO_1(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 6.087
datapathcell4 U(1,3) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.450
Clock Clock path delay 0.000
+ emFile_1_Clock_1
Source Destination Delay (ns)
\emFile_1:miso0(0)_PAD\ \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/route_si 16.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 \emFile_1:miso0(0)_PAD\ \emFile_1:miso0(0)_PAD\ \emFile_1:miso0(0)\/pad_in 0.000
iocell27 P12[7] 1 \emFile_1:miso0(0)\ \emFile_1:miso0(0)\/pad_in \emFile_1:miso0(0)\/fb 7.271
Route 1 \emFile_1:Net_16\ \emFile_1:miso0(0)\/fb \emFile_1:SPI0:BSPIM:sR8:Dp:u0\/route_si 7.103
datapathcell5 U(2,2) 1 \emFile_1:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.450
Clock Clock path delay 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\DataOut:Sync:ctrl_reg\/control_0 DB(0)_PAD:out 23.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_0 1.435
Route 1 Net_241_0 \DataOut:Sync:ctrl_reg\/control_0 DB(0)/pin_input 6.297
iocell8 P15[3] 1 DB(0) DB(0)/pin_input DB(0)/pad_out 15.486
Route 1 DB(0)_PAD DB(0)/pad_out DB(0)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_4 DB(4)_PAD:out 23.121
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_4 1.435
Route 1 Net_241_4 \DataOut:Sync:ctrl_reg\/control_4 DB(4)/pin_input 6.525
iocell12 P3[7] 1 DB(4) DB(4)/pin_input DB(4)/pad_out 15.161
Route 1 DB(4)_PAD DB(4)/pad_out DB(4)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_1 DB(1)_PAD:out 22.910
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_1 1.435
Route 1 Net_241_1 \DataOut:Sync:ctrl_reg\/control_1 DB(1)/pin_input 6.371
iocell9 P15[2] 1 DB(1) DB(1)/pin_input DB(1)/pad_out 15.104
Route 1 DB(1)_PAD DB(1)/pad_out DB(1)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_5 DB(5)_PAD:out 22.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_5 1.435
Route 1 Net_241_5 \DataOut:Sync:ctrl_reg\/control_5 DB(5)/pin_input 6.553
iocell13 P3[6] 1 DB(5) DB(5)/pin_input DB(5)/pad_out 14.591
Route 1 DB(5)_PAD DB(5)/pad_out DB(5)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_6 DB(6)_PAD:out 22.474
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_6 1.435
Route 1 Net_241_6 \DataOut:Sync:ctrl_reg\/control_6 DB(6)/pin_input 5.701
iocell14 P3[5] 1 DB(6) DB(6)/pin_input DB(6)/pad_out 15.338
Route 1 DB(6)_PAD DB(6)/pad_out DB(6)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_7 DB(7)_PAD:out 22.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_7 1.435
Route 1 Net_241_7 \DataOut:Sync:ctrl_reg\/control_7 DB(7)/pin_input 5.810
iocell15 P3[4] 1 DB(7) DB(7)/pin_input DB(7)/pad_out 14.987
Route 1 DB(7)_PAD DB(7)/pad_out DB(7)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_3 DB(3)_PAD:out 22.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_3 1.435
Route 1 Net_241_3 \DataOut:Sync:ctrl_reg\/control_3 DB(3)/pin_input 6.328
iocell11 P15[0] 1 DB(3) DB(3)/pin_input DB(3)/pad_out 14.255
Route 1 DB(3)_PAD DB(3)/pad_out DB(3)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_2 DB(2)_PAD:out 21.331
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_2 1.435
Route 1 Net_241_2 \DataOut:Sync:ctrl_reg\/control_2 DB(2)/pin_input 5.467
iocell10 P15[1] 1 DB(2) DB(2)/pin_input DB(2)/pad_out 14.429
Route 1 DB(2)_PAD DB(2)/pad_out DB(2)_PAD:out 0.000
Clock Clock path delay 0.000
+ SPIM_1_Clock
Source Destination Delay (ns)
Net_23/q MOSI_1(0)_PAD 24.096
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(2,3) 1 Net_23 Net_23/clock_0 Net_23/q 0.875
Route 1 Net_23 Net_23/q MOSI_1(0)/pin_input 7.784
iocell21 P2[3] 1 MOSI_1(0) MOSI_1(0)/pin_input MOSI_1(0)/pad_out 15.437
Route 1 MOSI_1(0)_PAD MOSI_1(0)/pad_out MOSI_1(0)_PAD 0.000
Clock Clock path delay 0.000
Net_25/q SCLK_1(0)_PAD 23.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell54 U(0,2) 1 Net_25 Net_25/clock_0 Net_25/q 0.875
Route 1 Net_25 Net_25/q SCLK_1(0)/pin_input 6.917
iocell20 P2[2] 1 SCLK_1(0) SCLK_1(0)/pin_input SCLK_1(0)/pad_out 15.787
Route 1 SCLK_1(0)_PAD SCLK_1(0)/pad_out SCLK_1(0)_PAD 0.000
Clock Clock path delay 0.000
Net_638/q SS_1(0)_PAD 22.516
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell59 U(0,3) 1 Net_638 Net_638/clock_0 Net_638/q 0.875
Route 1 Net_638 Net_638/q SS_1(0)/pin_input 5.988
iocell23 P2[5] 1 SS_1(0) SS_1(0)/pin_input SS_1(0)/pad_out 15.653
Route 1 SS_1(0)_PAD SS_1(0)/pad_out SS_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_Clock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 33.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(3,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 0.875
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_273/main_0 8.345
macrocell20 U(1,3) 1 Net_273 Net_273/main_0 Net_273/q 2.345
Route 1 Net_273 Net_273/q Tx_1(0)/pin_input 5.861
iocell17 P2[0] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.667
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ emFile_1_Clock_1
Source Destination Delay (ns)
\emFile_1:SPI0:BSPIM:state_0\/q \emFile_1:mosi0(0)_PAD\ 35.309
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell65 U(3,5) 1 \emFile_1:SPI0:BSPIM:state_0\ \emFile_1:SPI0:BSPIM:state_0\/clock_0 \emFile_1:SPI0:BSPIM:state_0\/q 0.875
Route 1 \emFile_1:SPI0:BSPIM:state_0\ \emFile_1:SPI0:BSPIM:state_0\/q \emFile_1:Net_10\/main_2 7.593
macrocell33 U(2,0) 1 \emFile_1:Net_10\ \emFile_1:Net_10\/main_2 \emFile_1:Net_10\/q 2.345
Route 1 \emFile_1:Net_10\ \emFile_1:Net_10\/q \emFile_1:mosi0(0)\/pin_input 9.622
iocell26 P2[7] 1 \emFile_1:mosi0(0)\ \emFile_1:mosi0(0)\/pin_input \emFile_1:mosi0(0)\/pad_out 14.874
Route 1 \emFile_1:mosi0(0)_PAD\ \emFile_1:mosi0(0)\/pad_out \emFile_1:mosi0(0)_PAD\ 0.000
Clock Clock path delay 0.000
\emFile_1:Net_22\/q \emFile_1:sclk0(0)_PAD\ 23.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(2,4) 1 \emFile_1:Net_22\ \emFile_1:Net_22\/clock_0 \emFile_1:Net_22\/q 0.875
Route 1 \emFile_1:Net_22\ \emFile_1:Net_22\/q \emFile_1:sclk0(0)\/pin_input 7.368
iocell28 P2[6] 1 \emFile_1:sclk0(0)\ \emFile_1:sclk0(0)\/pin_input \emFile_1:sclk0(0)\/pad_out 15.124
Route 1 \emFile_1:sclk0(0)_PAD\ \emFile_1:sclk0(0)\/pad_out \emFile_1:sclk0(0)_PAD\ 0.000
Clock Clock path delay 0.000
+ Clock To Output Enable Section
+ CyBUS_CLK
Source Destination Type Delay (ns)
CS(0)_SYNC/out DB(6)_PAD:out TURN ON 33.153
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(6)/oe 9.272
iocell14 P3[5] 1 DB(6) DB(6)/oe DB(6)/pad_out 17.787
Route 1 DB(6)_PAD DB(6)/pad_out DB(6)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(6)_PAD:out TURN OFF 33.153
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(6)/oe 9.272
iocell14 P3[5] 1 DB(6) DB(6)/oe DB(6)/pad_out 17.787
Route 1 DB(6)_PAD DB(6)/pad_out DB(6)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(4)_PAD:out TURN ON 32.685
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(4)/oe 9.272
iocell12 P3[7] 1 DB(4) DB(4)/oe DB(4)/pad_out 17.319
Route 1 DB(4)_PAD DB(4)/pad_out DB(4)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(4)_PAD:out TURN OFF 32.685
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(4)/oe 9.272
iocell12 P3[7] 1 DB(4) DB(4)/oe DB(4)/pad_out 17.319
Route 1 DB(4)_PAD DB(4)/pad_out DB(4)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(5)_PAD:out TURN ON 32.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(5)/oe 9.272
iocell13 P3[6] 1 DB(5) DB(5)/oe DB(5)/pad_out 17.282
Route 1 DB(5)_PAD DB(5)/pad_out DB(5)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(5)_PAD:out TURN OFF 32.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(5)/oe 9.272
iocell13 P3[6] 1 DB(5) DB(5)/oe DB(5)/pad_out 17.282
Route 1 DB(5)_PAD DB(5)/pad_out DB(5)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(7)_PAD:out TURN ON 32.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(7)/oe 9.272
iocell15 P3[4] 1 DB(7) DB(7)/oe DB(7)/pad_out 16.646
Route 1 DB(7)_PAD DB(7)/pad_out DB(7)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(7)_PAD:out TURN OFF 32.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(7)/oe 9.272
iocell15 P3[4] 1 DB(7) DB(7)/oe DB(7)/pad_out 16.646
Route 1 DB(7)_PAD DB(7)/pad_out DB(7)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(0)_PAD:out TURN ON 30.629
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(0)/oe 6.614
iocell8 P15[3] 1 DB(0) DB(0)/oe DB(0)/pad_out 17.921
Route 1 DB(0)_PAD DB(0)/pad_out DB(0)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(0)_PAD:out TURN OFF 30.629
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(0)/oe 6.614
iocell8 P15[3] 1 DB(0) DB(0)/oe DB(0)/pad_out 17.921
Route 1 DB(0)_PAD DB(0)/pad_out DB(0)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(3)_PAD:out TURN ON 30.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(3)/oe 6.614
iocell11 P15[0] 1 DB(3) DB(3)/oe DB(3)/pad_out 17.880
Route 1 DB(3)_PAD DB(3)/pad_out DB(3)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(3)_PAD:out TURN OFF 30.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(3)/oe 6.614
iocell11 P15[0] 1 DB(3) DB(3)/oe DB(3)/pad_out 17.880
Route 1 DB(3)_PAD DB(3)/pad_out DB(3)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(1)_PAD:out TURN ON 30.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(1)/oe 6.614
iocell9 P15[2] 1 DB(1) DB(1)/oe DB(1)/pad_out 17.490
Route 1 DB(1)_PAD DB(1)/pad_out DB(1)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(1)_PAD:out TURN OFF 30.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(1)/oe 6.614
iocell9 P15[2] 1 DB(1) DB(1)/oe DB(1)/pad_out 17.490
Route 1 DB(1)_PAD DB(1)/pad_out DB(1)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(2)_PAD:out TURN ON 29.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(2)/oe 6.614
iocell10 P15[1] 1 DB(2) DB(2)/oe DB(2)/pad_out 17.163
Route 1 DB(2)_PAD DB(2)/pad_out DB(2)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(2)_PAD:out TURN OFF 29.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.039
macrocell3 U(0,1) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(2)/oe 6.614
iocell10 P15[1] 1 DB(2) DB(2)/oe DB(2)/pad_out 17.163
Route 1 DB(2)_PAD DB(2)/pad_out DB(2)_PAD:out 0.000
Clock Clock path delay 0.000