Static Timing Analysis

Project : Catcher
Build Time : 08/03/17 10:05:56
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 54.726 MHz
UART_1_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 54.726 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 54.726 MHz 18.273 23.394
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.118
macrocell2 U(0,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell1 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 78.914 MHz 12.672 28.995
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.118
macrocell12 U(0,4) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 78.914 MHz 12.672 28.995
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.118
macrocell13 U(0,4) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 84.825 MHz 11.789 29.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.235
macrocell9 U(0,3) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 84.825 MHz 11.789 29.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.235
macrocell14 U(0,3) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 84.998 MHz 11.765 29.902
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.211
macrocell6 U(0,3) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 84.998 MHz 11.765 29.902
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.211
macrocell15 U(0,3) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 56.139 MHz 17.813 13023.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 4.957
macrocell1 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.896
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_1\/q \UART_1:BUART:sRX:RxBitCounter\/load 58.596 MHz 17.066 13024.601
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,3) 1 \UART_1:BUART:rx_state_1\ \UART_1:BUART:rx_state_1\/clock_0 \UART_1:BUART:rx_state_1\/q 1.250
Route 1 \UART_1:BUART:rx_state_1\ \UART_1:BUART:rx_state_1\/q \UART_1:BUART:rx_counter_load\/main_0 4.210
macrocell1 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.896
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 59.687 MHz 16.754 13024.913
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,3) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 3.898
macrocell1 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.896
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 59.830 MHz 16.714 13024.953
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,3) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 3.858
macrocell1 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.896
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 76.982 MHz 12.990 13028.677
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,4) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 2.629
macrocell2 U(0,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell1 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 77.083 MHz 12.973 13028.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 2.612
macrocell2 U(0,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell1 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 78.321 MHz 12.768 13028.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 5.508
datapathcell1 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 79.643 MHz 12.556 13029.111
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,4) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 7.796
macrocell8 U(1,3) 1 \UART_1:BUART:rx_state_3\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 83.077 MHz 12.037 13029.630
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.290
macrocell3 U(0,4) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 2.317
statusicell1 U(0,4) 1 \UART_1:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_load_fifo\/main_2 83.368 MHz 11.995 13029.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,4) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_load_fifo\/main_2 7.235
macrocell7 U(0,3) 1 \UART_1:BUART:rx_load_fifo\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 8.255
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.211
macrocell6 U(0,3) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 8.255
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.211
macrocell15 U(0,3) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 8.279
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.235
macrocell9 U(0,3) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 8.279
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.235
macrocell14 U(0,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 9.162
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.118
macrocell12 U(0,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 9.162
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.118
macrocell13 U(0,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 14.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 3.044
Route 1 Net_9 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.118
macrocell2 U(0,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.291
datapathcell1 U(0,4) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.182
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,3) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.932
statusicell1 U(0,4) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 3.504
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_1:BUART:rx_count_0\ \UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.884
macrocell10 U(0,4) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 3.509
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.889
macrocell10 U(0,4) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 3.509
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 2.889
macrocell12 U(0,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_0\/main_0 3.509
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_0\/main_0 2.889
macrocell13 U(0,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 3.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.894
macrocell10 U(0,4) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 3.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 2.894
macrocell12 U(0,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_0\/main_1 3.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_0\/main_1 2.894
macrocell13 U(0,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_3\/main_3 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,3) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
macrocell8 U(1,3) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_3\/main_3 2.292
macrocell8 U(1,3) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 3.569
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,3) 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/clock_0 \UART_1:BUART:rx_last\/q 1.250
Route 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 2.319
macrocell9 U(0,3) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000